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? semiconductor components industries, llc, 2001 january, 2001 rev. 7 1 publication order number: cs8156/d cs8156 12 v, 5.0 v low dropout dual regulator with enable the cs8156 is a low dropout 12 v/5.0 v dual output linear regulator. the 12 v 5.0% output sources 750 ma and the 5.0 v 2.0% output sources 100 ma. the on board enable function controls the regulator's two outputs. when the enable lead is low, the regulator is placed in sleep mode. both outputs are disabled and the regulator draws only 200 na of quiescent current. the regulator is protected against overvoltage conditions. both outputs are protected against short circuit and thermal runaway conditions. the cs8156 is packaged in a 5 lead to220 with copper tab. the copper tab can be connected to a heat sink if necessary. features ? two regulated outputs 12 v 5.0%; 750 ma 5.0 v 2.0%; 100 ma ? very low sleep mode current drain 200 na ? fault protection reverse battery +60 v, 50 v peak transient voltage short circuit thermal shutdown ? cmos compatible enable http://onsemi.com pin connections and marking diagram device package shipping ordering information 50 units/rail cs8156yt5 to220* straight 50 units/rail cs8156ytva5 to220* vertical 50 units/rail cs8156ytha5 to220* horizontal cs8156 awlyww 1 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week to220 five lead t suffix case 314d 1 5 to220 five lead tva suffix case 314k to220 five lead tha suffix case 314a 1 5 1 *five lead. tab = gnd pin 1. v in 2. v out1 3. gnd 4. enable 5. v out2
cs8156 http://onsemi.com 2 figure 1. block diagram v out2 , 5.0 v antisaturation and current limit + + overvoltage shutdown bandgap reference thermal shutdown preregulator v in v out1 , 12 v enable gnd antisaturation and current limit + absolute maximum ratings* rating value unit input voltage: operating range peak transient voltage (note 1.) 0.5 to 26 60 v v internal power dissipation internally limited operating temperature range 40 to +125 c junction temperature range 40 to +150 c storage temperature range 65 to +150 c lead temperature soldering: wave solder (through hole styles only) (note 2.) 260 peak c 1. load dump = 46 v 2. 10 second maximum. *the maximum package power dissipation must be observed.
cs8156 http://onsemi.com 3 electrical characteristics for v out: (v in = 14.5 v, i out1 = 5.0 ma, i out2 = 5.0 ma, 40 c t j +150 c, 40 c t c +125 c; unless otherwise specified.) characteristic test conditions min typ max unit output stage (v out1 ) output voltage, (v out1 ) 13 v v in 16 v, i out1 750 ma 11.2 12.0 12.8 v dropout voltage i out1 = 500 ma i out1 = 750 ma 0.4 0.6 0.6 1.0 v v line regulation 13 v v in 16 v, 5.0 ma i out1 < 100 ma 15 80 mv load regulation 5.0 ma i out1 500 ma 15 80 mv quiescent current i out1 500 ma, no load on standby i out1 750 ma, no load on standby 45 100 125 250 ma ma quiescent current (sleep mode) enable = low 0.2 50 m a ripple rejection f = 120 hz, i out = 5.0 ma, v in = 1.5 v pp at 15.5 v dc 42 70 db current limit 0.75 1.20 2.50 a maximum line transient v out1 13 v 60 90 v reverse polarity input voltage, dc v out1 0.6 v, 10 w load 18 30 v reverse polarity input voltage, transient 1.0% duty cycle, t = 100 ms, v out 6.0 v, 10 w load 50 80 v output noise voltage 10 hz 100 khz 500 m vrms output impedance 500 ma dc and 10 ma rms, 100hz 0.2 1.0 w overvoltage shutdown 28 34 45 v standby output (v out2 ) output voltage, (v out2 ) 9.0 v v in 16 v, 1.0 ma i out2 100 ma 4.90 5.00 5.10 v dropout voltage i out2 100 ma 0.60 v line regulation 6.0 v v in 26 v, 1.0 ma i out 100 ma 5.0 50 mv load regulation 1.0 ma i out2 100 ma; 9.0 v v in 16 v 5.0 50 mv ripple rejection f = 120 hz; i out = 100 ma, v in = 1.5 v pp at 14.5 v dc 42 70 db current limit 100 200 ma enable function (enable) input enable threshold v out1 off v out1 on 2.00 1.25 1.25 0.80 v v input enable current v enable v threshold 10 0 10 m a package pin description package lead # 5 lead to220 lead symbol function 1 v in supply voltage, usually direct from battery. 2 v out1 regulated output 12 v, 750 ma (typ). 3 gnd ground connection. 4 enable cmos compatible input lead; switches outputs on and off. when enable is high v out1 and v out2 are active. 5 v out2 regulated output 5.0 v, 100 ma (typ).
cs8156 http://onsemi.com 4 typical performance characteristics 2000 1800 1600 1400 1200 1000 800 600 400 200 0 0 50 100 150 200 i out (ma) input voltage (v) figure 2. dropout voltage vs. i out2 figure 3. v out1 vs. input voltage temp ( c) temp ( c) figure 4. v out1 vs. temperature figure 5. v out2 vs. temperature 12 40 dropout voltage (mv) output voltage (v) 5.030 v out1 (v) v out2 (v) 12.15 40 20 v enable (v) v enable (v) figure 6. enable current vs. enable voltage figure 7. enable current vs. enable voltage i enable ( m a) i enable (ma) 0 0 5.0 100 13 11 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 1.0 2.0 20 0 20 40 60 12.10 12.05 12.00 11.95 11.90 11.85 11.80 11.75 20 0 20 40 60 80 100 120 140 160 5.020 5.010 5.000 4.990 4.980 4.970 40 0 20 40 60 80 100 120 140 16 0 80 60 40 20 0 1.0 2.0 3.0 4.0 5.0 4.0 3.0 2.0 1.0 0 5.0 10 15 20 25 r l = 10 w
cs8156 http://onsemi.com 5 typical performance characteristics (continued) time ( m s) time ( m s) figure 8. line transient response (v out1 ) figure 9. line transient response (v out2 ) time ( m s) figure 10. load transient response (v out1 ) figure 11. load transient response (v out2 ) 10 input voltage change (v) input voltage chnage (v) load current (a) standby load current (ma) 150 ambient temperature ( c) output current (ma) figure 12. maximum power dissipation (to220) figure 13. quiescent current vs. output current for v out2 power dissipation (w) quiescent current (ma) 0 0 150 20 10 output voltage deviation (mv) output voltage deviation (mv) output voltage deviation (mv) standby output voltage deviation (mv) 20 0 10 20 3.0 2.0 1.0 0 0 102030405060 5.0 0 5.0 10 3.0 2.0 1.0 0 0 102030405060 100 50 0 50 100 150 0.8 0.6 0.4 0.2 0 0 102030405060 time ( m s) 150 100 50 0 50 100 150 20 15 10 5.0 0 0 102030405060 18 16 14 12 10 8.0 6.0 4.0 2.0 0 10 20 30 40 50 60 70 80 90 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 100 200 300 400 500 600 700 800 i out2 = 100 ma i out1 = 500 ma infinite heat sink 10 c/w heat sink no heat sink no load on 5.0 v v in = 14 v 125 c 25 c 40 c
cs8156 http://onsemi.com 6 typical performance characteristics (continued) 0 output current (ma) output current (ma) figure 14. quiescent current vs. output current for v out1 figure 15. line regulation vs. output current for v out2 output current (ma) output current (ma) figure 16. load regulation vs. output current fo v out2 figure 17. line regulation vs. output current for v out1 3.0 0 quiescent current (ma) line regulation (mv) 25 load regulation (mv) line regulation (mv) 0 0 output current (ma) figure 18. load regulation vs. output current for v out1 load regulation (mv) 0 0 0 22 20 18 16 14 12 10 8.0 6.0 4.0 2.0 0 20 40 60 80 100 120 140 2.0 1.0 0 1.0 2.0 3.0 4.0 5.0 6.0 20 40 60 80 100 120 140 2.0 4.0 6.0 8.0 10 12 14 16 18 20 40 60 80 100 120 140 20 15 10 5.0 0 5.0 10 15 20 25 30 35 40 100 200 300 400 500 600 700 800 5.0 10 15 20 25 30 35 40 100 200 300 400 500 600 700 800 no load on 5.0 v v in = 14 v 125 c 25 c 40 c 125 c 25 c 40 c v in = 6.026 v 40 c 25 c 125 c v in = 14 v 40 c 25 c 125 c v in = 14 v 40 c 125 c 25 c v in = 1326v
cs8156 http://onsemi.com 7 definition of terms dropout voltage the inputoutput voltage differential at which the circuit ceases to regulate against further reduction in input voltage. measured when the output voltage has dropped 100 mv from the nominal value obtained at 14 v input, dropout voltage is dependent upon load current and junction temperature. input voltage the dc voltage applied to the input terminals with respect to ground. input output differential the voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. line regulation the change in output voltage for a change in the input voltage. the measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. load regulation the change in output voltage for a change in load current at constant chip temperature. long term stability output voltage stability under accelerated lifetest conditions after 1000 hours with maximum rated voltage and junction temperature. output noise voltage the rms ac voltage at the output, with constant load and no input ripple, measured over a specified frequency range. quiescent current the part of the positive input current that does not contribute to the positive load current, i.e., the regulator ground lead current. ripple rejection the ratio of the peaktopeak input ripple voltage to the peaktopeak output ripple voltage. temperature stability of v out the percentage change in output voltage for a thermal variation from room temperature to either temperature extreme. figure 19. typical circuit waveform 14 v 0 v 0 v 2.0 v 0.8 v v in enable v out1 v out2 60 v 12 v 5.0 v 34 v 12 v 2.4 v 3.0 v 26 v 12 v 0 v 12 v 5.0 v 12 v 14v 0 v load dump low v in line noise, etc. v out1 short circuit v out1 thermal shutdown turn off turn on 2.4 v v out2 short circuit application notes stability considerations the output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the cheapest solution, but, if the circuit operates at low temperatures (25 c to 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provides this information. the value for the output capacitors c2 and c3 shown in the test and applications circuit should work for most applications, however it is not necessarily the best solution. to determine acceptable values for c2 and c3 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part for each output. step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor c 2 will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscillations
cs8156 http://onsemi.com 8 are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage conditions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capacitor will usually cost less and occupy less board space. if the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: raise the temperature to the highest specified operating temperature. v ary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found for each output, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitors should be less than 50% of the maximum allowable esr found in step 3 above. repeat steps 1 through 7 with c 3 , the capacitor on the other output. calculating power dissipation in a dual output linear regulator the maximum power dissipation for a dual output regulator (figure 20) is p d(max) v in(max) v out1(min) i out1(max) v in(max) v out2(min) i out2(max) v in(max) iq (1) where: v in(max) is the maximum input voltage, v out1(min) is the minimum output voltage from v out1 , v out2(min) is the minimum output voltage from v out2 , i out1(max) is the maximum output current, for the application, i out2(max) is the maximum output current, for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r q ja can be calculated: r ja 150 c t a p d (2) the value of r q ja can be compared with those in the package section of the data sheet. those packages with r q ja 's less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. figure 20. dual output regulator with key performance parameters labeled. smart regulator control features v out1 i out1 v out2 i out2 v in i in i q heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r q ja : r ja r jc r cs r sa (3) where: r q jc = the junctiontocase thermal resistance, r q cs = the casetoheatsink thermal resistance, and r q sa = the heatsinktoambient thermal resistance. r q jc appears in the package section of the data sheet. like r q ja , it too is a function of package type. r q cs and r q sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
cs8156 http://onsemi.com 9 figure 21. test & application circuit cs8156 v out1 v out2 enable gnd v in + + * c 1 is required if the regulator is far from power supply filter. ** c 2, c 3 required for stability. c 1 * 0.1 m f c 2 ** 22 m f c 3 ** 22 m f
cs8156 http://onsemi.com 10 package dimensions to220 five lead t suffix case 314d04 issue e q 12345 u k d g a b 5 pl j h l e c m q m 0.356 (0.014) t seating plane t dim min max min max millimeters inches a 0.572 0.613 14.529 15.570 b 0.390 0.415 9.906 10.541 c 0.170 0.180 4.318 4.572 d 0.025 0.038 0.635 0.965 e 0.048 0.055 1.219 1.397 g 0.067 bsc 1.702 bsc h 0.087 0.112 2.210 2.845 j 0.015 0.025 0.381 0.635 k 0.990 1.045 25.146 26.543 l 0.320 0.365 8.128 9.271 q 0.140 0.153 3.556 3.886 u 0.105 0.117 2.667 2.972 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. to220 five lead tva suffix case 314k01 issue o notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. dim min max min max millimeters inches a 0.560 0.590 14.22 14.99 b 0.385 0.415 9.78 10.54 c 0.160 0.190 4.06 4.83 d 0.027 0.037 0.69 0.94 e 0.045 0.055 1.14 1.40 f 0.530 0.545 13.46 13.84 g 0.067 bsc 1.70 bsc j 0.014 0.022 0.36 0.56 k 0.785 0.800 19.94 20.32 l 0.321 0.337 8.15 8.56 m 0.063 0.078 1.60 1.98 q 0.146 0.156 3.71 3.96 s 0.146 0.196 3.71 4.98 u 0.460 0.475 11.68 12.07 w 55 r 0.271 0.321 6.88 8.15 a u d g b t m 0.356 (0.014) m q 5 pl q k f j c e t s l 12345 seating plane r m w
cs8156 http://onsemi.com 11 to220 five lead tha suffix case 314a03 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 0.043 (1.092) maximum. dim a min max min max millimeters 0.572 0.613 14.529 15.570 inches b 0.390 0.415 9.906 10.541 c 0.170 0.180 4.318 4.572 d 0.025 0.038 0.635 0.965 e 0.048 0.055 1.219 1.397 f 0.570 0.585 14.478 14.859 g 0.067 bsc 1.702 bsc j 0.015 0.025 0.381 0.635 k 0.730 0.745 18.542 18.923 l 0.320 0.365 8.128 9.271 q 0.140 0.153 3.556 3.886 s 0.210 0.260 5.334 6.604 u 0.468 0.505 11.888 12.827 t seating plane l s e c f k j optional chamfer 5x d 5x m p m 0.014 (0.356) t g a u b q p package thermal data parameter to220 five lead unit r q jc typical 2.0 c/w r q ja typical 50 c/w
cs8156 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs8156/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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